Mutually Aware Prefetcher and On-Chip Network Designs for Multi-Cores

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Hardware prefetching has become an essential technique in high performance processors to hide long external memory latencies. In multi-core architectures with cores communicating through a shared on-chip network, traffic generated by the prefetchers can account for up to 60% of the total on-chip network traffic. However, the distinct characteristics of prefetch traffic have not been considered in on-chip network design. In addition, prefetchers have been oblivious to the network congestion. In this work, we investigate the interactions between prefetchers and on-chip networks, exploiting the synergy of these two components in multi-cores. Firstly, we explore the design space of prefetch-aware on-chip networks. Considering the difference between prefetch and non-prefetch packets, we propose a priority-based router design, which selects non-prefetch packets first over prefetch packets. Secondly, we investigate network-aware prefetcher designs. We propose a prefetch control mechanism sensitive to network congestion-throttling prefetch requests based on the current network congestion. Our evaluation with full system simulations shows that the combination of the proposed prefetch-aware router and congestion-sensitive prefetch control improves the performance of benchmark applications by 11-12% with out-of-order cores, and 21-22% with SMT cores on average, up to 37% on some of the workloads.
Publisher
IEEE COMPUTER SOC
Issue Date
2014-09
Language
English
Article Type
Article
Keywords

INTERCONNECTION NETWORKS; FLOW-CONTROL; PERFORMANCE; MULTIPROCESSORS

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.63, no.9, pp.2316 - 2329

ISSN
0018-9340
DOI
10.1109/TC.2013.99
URI
http://hdl.handle.net/10203/191276
Appears in Collection
EE-Journal Papers(저널논문)CS-Journal Papers(저널논문)
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