Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement

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Many-core processors will have many processing cores with a network-on-chip (NoC) that provides access to shared resources such as main memory and on-chip caches. However, locally-fair arbitration in multi-stage NoC can lead to globally unfair access to shared resources and impact system-level performance depending on where each task is physically placed. In this work, we propose an arbitration to provide equality-of-service (EoS) in the network and provide support for location-oblivious task placement. We propose using probabilistic arbitration combined with distance-based weights to achieve EoS and overcome the limitation of round-robin arbiter. However, the complexity of probabilistic arbitration results in high area and long latency which negatively impacts performance. In order to reduce the hardware complexity, we propose an hybrid arbiter that switches between a simple arbiter at low load and a complex arbiter at high load. The hybrid arbiter is enabled by the observation that arbitration only impacts the overall performance and global fairness at a high load. We evaluate our arbitration scheme with synthetic traffic patterns and GPGPU benchmarks. Our results shows that hybrid arbiter that combines round-robin arbiter with probabilistic distance-based arbitration reduces performance variation as task placement is varied and also improves average IPC.
Publisher
IEEE COMPUTER SOC
Issue Date
2014-06
Language
English
Article Type
Article
Keywords

QUALITY-OF-SERVICE; INTERCONNECTION NETWORKS; ARCHITECTURE; PERFORMANCE; ROUTER

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.63, no.6, pp.1486 - 1499

ISSN
0018-9340
DOI
10.1109/TC.2012.241
URI
http://hdl.handle.net/10203/189641
Appears in Collection
EE-Journal Papers(저널논문)
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