A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization

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A highly linear LNA is implemented in a 0.18 mu m SOI CMOS process for 1 GHz SAW-less receiver applications. To achieve lower noise figure (NF) than conventional simultaneous noise and input matching methods, a capacitive loading based simultaneous noise and input matching technique reducing the NF degradation coming from a lossy gate inductor has been devised. In addition, in order to improve both the 1 dB gain compression point (CP1dB) and the third-order intercept point (IP3) without sacrificing NF, a large-signal transconductance linearization method adopting body-bias control and complementary-superposition is proposed. The proposed LNA shows a measured input-referred CP1dB of 3 dBm, 1 dB desensitization point (B1dB) of 0 dBm and IB (in-band)-IIP3 of 22 dBm with gain of 10.7 dB and NF of 1.3 dB at 1 GHz while driving a 50 Omega load impedance. It draws 20 mA with a buffer stage from a 2.5 V supply voltage.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2014-06
Language
English
Article Type
Article
Keywords

WIRELESS RECEIVERS; LNA

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.6, pp.1286 - 1302

ISSN
0018-9200
DOI
10.1109/JSSC.2014.2319262
URI
http://hdl.handle.net/10203/189637
Appears in Collection
EE-Journal Papers(저널논문)
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