An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177-mu W ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm x 4 mm and that of the PLL is 0.4 mm x 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a frequency offset of 70 kHz and fluctuation of +/- 75 kHz (the maximum frequency error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 mu W from a 1.2-V supply voltage.