A High-Linearity Low-Noise Reconfiguration-Based Programmable Gain Amplifier

Abstract

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in 0.18-mu m CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than +/- 0.33 dB, an IIP3 of 7.4 similar to 14.5 dBm, a P1dB of -7 similar to 1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of 0.04 mm(2) and consumes only 1.3 mA from the 1.8 V supply.