DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yang, JH | ko |
dc.contributor.author | Kim, BW | ko |
dc.contributor.author | Nam, SJ | ko |
dc.contributor.author | Kwon, YS | ko |
dc.contributor.author | Lee, DH | ko |
dc.contributor.author | Lee, JY | ko |
dc.contributor.author | Hwang, CS | ko |
dc.contributor.author | Lee, Yong-Hoon | ko |
dc.contributor.author | Hwang, SH | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.contributor.author | Kyung, Chong-Min | ko |
dc.date.accessioned | 2009-11-05T02:28:34Z | - |
dc.date.available | 2009-11-05T02:28:34Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2000-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.8, no.2, pp.173 - 183 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/12149 | - |
dc.description.abstract | This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications, The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored, Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | MetaCore: An application-specific programmable DSP development system | - |
dc.type | Article | - |
dc.identifier.wosid | 000086495400006 | - |
dc.identifier.scopusid | 2-s2.0-0033903887 | - |
dc.type.rims | ART | - |
dc.citation.volume | 8 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 173 | - |
dc.citation.endingpage | 183 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Yong-Hoon | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.nonIdAuthor | Yang, JH | - |
dc.contributor.nonIdAuthor | Kim, BW | - |
dc.contributor.nonIdAuthor | Nam, SJ | - |
dc.contributor.nonIdAuthor | Kwon, YS | - |
dc.contributor.nonIdAuthor | Lee, DH | - |
dc.contributor.nonIdAuthor | Lee, JY | - |
dc.contributor.nonIdAuthor | Hwang, CS | - |
dc.contributor.nonIdAuthor | Hwang, SH | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | application-specific instruction-set processor | - |
dc.subject.keywordAuthor | (ASIP) | - |
dc.subject.keywordAuthor | design efficiency | - |
dc.subject.keywordAuthor | design turnaround time | - |
dc.subject.keywordAuthor | digital signal processor | - |
dc.subject.keywordAuthor | processor specification | - |
dc.subject.keywordAuthor | retargetable compilation | - |
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