DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kwak, Sanghoon | ko |
dc.contributor.author | Lee, Jeong-Gun | ko |
dc.contributor.author | Jung, Eun-Gu | ko |
dc.contributor.author | Har, Dongsoo | ko |
dc.contributor.author | Ercegovac, Milos D | ko |
dc.contributor.author | (Lee, Jeong-A | ko |
dc.date.accessioned | 2013-03-12T22:09:24Z | - |
dc.date.available | 2013-03-12T22:09:24Z | - |
dc.date.created | 2013-01-10 | - |
dc.date.created | 2013-01-10 | - |
dc.date.issued | 2009-06 | - |
dc.identifier.citation | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.18, no.4, pp.787 - 800 | - |
dc.identifier.issn | 0218-1266 | - |
dc.identifier.uri | http://hdl.handle.net/10203/103678 | - |
dc.description.abstract | The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder. | - |
dc.language | English | - |
dc.publisher | WORLD SCIENTIFIC PUBL CO PTE LTD | - |
dc.title | EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING | - |
dc.type | Article | - |
dc.identifier.wosid | 000266614200009 | - |
dc.identifier.scopusid | 2-s2.0-67650245354 | - |
dc.type.rims | ART | - |
dc.citation.volume | 18 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 787 | - |
dc.citation.endingpage | 800 | - |
dc.citation.publicationname | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | - |
dc.contributor.localauthor | Har, Dongsoo | - |
dc.contributor.nonIdAuthor | Kwak, Sanghoon | - |
dc.contributor.nonIdAuthor | Lee, Jeong-Gun | - |
dc.contributor.nonIdAuthor | Jung, Eun-Gu | - |
dc.contributor.nonIdAuthor | Ercegovac, Milos D | - |
dc.contributor.nonIdAuthor | (Lee, Jeong-A | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Heterogeneous adder | - |
dc.subject.keywordAuthor | integer linear programming | - |
dc.subject.keywordAuthor | power-delay trade-off | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.