EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING

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The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder.
Publisher
WORLD SCIENTIFIC PUBL CO PTE LTD
Issue Date
2009-06
Language
English
Article Type
Article
Citation

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.18, no.4, pp.787 - 800

ISSN
0218-1266
URI
http://hdl.handle.net/10203/103678
Appears in Collection
GT-Journal Papers(저널논문)
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