Multiproduct Lot Merging-Splitting Algorithms for Semiconductor Wafer Fabrication

Cited 5 time in webofscience Cited 0 time in scopus
  • Hit : 786
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorBang, June-Youngko
dc.contributor.authorKim, Yeong-Daeko
dc.contributor.authorChoi, Seong-Wooko
dc.date.accessioned2013-03-12T08:47:00Z-
dc.date.available2013-03-12T08:47:00Z-
dc.date.created2012-07-18-
dc.date.created2012-07-18-
dc.date.issued2012-05-
dc.identifier.citationIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.25, no.2, pp.200 - 210-
dc.identifier.issn0894-6507-
dc.identifier.urihttp://hdl.handle.net/10203/101820-
dc.description.abstractThis paper focuses on a lot merging-splitting problem in a semiconductor wafer fabrication facility in which a relatively large number of wafer types are produced according to orders with different due dates. In the fab, two or more lots can be merged into a single lot if routes and all processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging-splitting algorithms to reduce the total tardiness of the orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectMULTIPLE-ORDERS-
dc.subjectDIFFUSION/OXIDATION PROCESSES-
dc.subjectJOB-
dc.subjectFACILITY-
dc.subjectSIMULATION-
dc.subjectMACHINES-
dc.subjectRELEASE-
dc.subjectRULE-
dc.titleMultiproduct Lot Merging-Splitting Algorithms for Semiconductor Wafer Fabrication-
dc.typeArticle-
dc.identifier.wosid000303999400011-
dc.identifier.scopusid2-s2.0-84860667869-
dc.type.rimsART-
dc.citation.volume25-
dc.citation.issue2-
dc.citation.beginningpage200-
dc.citation.endingpage210-
dc.citation.publicationnameIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING-
dc.identifier.doi10.1109/TSM.2012.2189784-
dc.contributor.localauthorKim, Yeong-Dae-
dc.contributor.nonIdAuthorBang, June-Young-
dc.contributor.nonIdAuthorChoi, Seong-Woo-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorLot merging and splitting-
dc.subject.keywordAuthorscheduling-
dc.subject.keywordAuthorsemiconductor wafer fabrication-
dc.subject.keywordAuthorsimulation-
dc.subject.keywordPlusMULTIPLE-ORDERS-
dc.subject.keywordPlusDIFFUSION/OXIDATION PROCESSES-
dc.subject.keywordPlusJOB-
dc.subject.keywordPlusFACILITY-
dc.subject.keywordPlusSIMULATION-
dc.subject.keywordPlusMACHINES-
dc.subject.keywordPlusRELEASE-
dc.subject.keywordPlusRULE-
Appears in Collection
IE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 5 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0