DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bang, June-Young | ko |
dc.contributor.author | Kim, Yeong-Dae | ko |
dc.contributor.author | Choi, Seong-Woo | ko |
dc.date.accessioned | 2013-03-12T08:47:00Z | - |
dc.date.available | 2013-03-12T08:47:00Z | - |
dc.date.created | 2012-07-18 | - |
dc.date.created | 2012-07-18 | - |
dc.date.issued | 2012-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.25, no.2, pp.200 - 210 | - |
dc.identifier.issn | 0894-6507 | - |
dc.identifier.uri | http://hdl.handle.net/10203/101820 | - |
dc.description.abstract | This paper focuses on a lot merging-splitting problem in a semiconductor wafer fabrication facility in which a relatively large number of wafer types are produced according to orders with different due dates. In the fab, two or more lots can be merged into a single lot if routes and all processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging-splitting algorithms to reduce the total tardiness of the orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MULTIPLE-ORDERS | - |
dc.subject | DIFFUSION/OXIDATION PROCESSES | - |
dc.subject | JOB | - |
dc.subject | FACILITY | - |
dc.subject | SIMULATION | - |
dc.subject | MACHINES | - |
dc.subject | RELEASE | - |
dc.subject | RULE | - |
dc.title | Multiproduct Lot Merging-Splitting Algorithms for Semiconductor Wafer Fabrication | - |
dc.type | Article | - |
dc.identifier.wosid | 000303999400011 | - |
dc.identifier.scopusid | 2-s2.0-84860667869 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 200 | - |
dc.citation.endingpage | 210 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | - |
dc.identifier.doi | 10.1109/TSM.2012.2189784 | - |
dc.contributor.localauthor | Kim, Yeong-Dae | - |
dc.contributor.nonIdAuthor | Bang, June-Young | - |
dc.contributor.nonIdAuthor | Choi, Seong-Woo | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Lot merging and splitting | - |
dc.subject.keywordAuthor | scheduling | - |
dc.subject.keywordAuthor | semiconductor wafer fabrication | - |
dc.subject.keywordAuthor | simulation | - |
dc.subject.keywordPlus | MULTIPLE-ORDERS | - |
dc.subject.keywordPlus | DIFFUSION/OXIDATION PROCESSES | - |
dc.subject.keywordPlus | JOB | - |
dc.subject.keywordPlus | FACILITY | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | MACHINES | - |
dc.subject.keywordPlus | RELEASE | - |
dc.subject.keywordPlus | RULE | - |
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