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A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; Park, Jun-Seok; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04 |
(A) low noise digital phase-locked loop with quantization noise suppression and loop delay reduction techniques = 양자화 잡음과 루프 지연시간을 줄이는 방법을 이용한 저잡음 디지털 위상고정루프link Han, Jae-Hyun; 한재현; et al, 한국과학기술원, 2010 |
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