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Showing results 1 to 4 of 4

1
A 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique

Wang, SH; Kim, J; Lee, J; Nam, HS; Kim, YG; Shim, JH; Ahn, HK; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.4, pp.648 - 657, 2001-04

2
A DLL-based frequency synthesizer with selective reuse of a delay cell scheme for 2.4 GHz ISM band

Kang, S; Kim, Beom-Sup, IEICE TRANSACTIONS ON ELECTRONICS, v.E88C, no.1, pp.149 - 153, 2005

3
A Low-Jitter Mixed-Mode DLL for Hign-Speed DRAM Applications

j. j. kim; s.-b. lee; t. -s. jung; c.-h. kim; s.-i. cho; b. kim, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.10, pp.1430 - 1436, 2000-10

4
분수 분주형 주파수고정루프 기반의 비동기 샘플링 테크닉을 이용한 완전 합성 가능 쿼드러쳐 신호 교정기 = A fully-synthesizable quadrature signal corrector using an asynchronous sampling technique with fractional frequency-locked looplink

이성규; Lee, Seong-Gyu; et al, 한국과학기술원, 2016

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